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1 v827464n24sc 2.5 volt 64m x 72 high performance registered ecc ddr sdram module v827464n24sc rev. 1.2 april 2006 features 184 pin registered 67,108,864 x 72 bit organization ddr sdram modules utilizes high performance 64m x 4 ddr sdram in tsopii-66 and fbga package single +2.5v ( 0.2v) power supply programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh all inputs, outputs are sstl-2 compatible 8192 refresh cycles every 64 ms serial presence detect (spd) ddr sdram performance description the v827464n24sc memory module is organized 67,108,864 x 72 bits in a 184 pin memory module. the 64m x 72 memory module uses 18 promos 64m x 4 ddr sdram. the x72 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. component used -6 -7 -75 -8 t ck clock frequency (max.) 166 (pc333) 143 (pc266a) 133 (pc266b) 125 (pc200) t ac clock access time cas latency = 2.5 677.58 module speed a1 pc1600 (100mhz @ cl2) b0 pc2100b (133mhz @ cl2.5) b1 pc2100a (133mhz @ cl2) c0 pc2700 (166mhz @ cl2.5) module speed d0 d3 c0 units clock frequency (max.) 200 (pc400a) 200 (pc400b) 166 (pc333) mhz t ck clock cycle time cas latency = 2 7.5 7.5 7.5 ns clock cycle time cas latency = 2.5 5 6 6 ns clock cycle time cas latency = 3 5 5 - ns t rcd trcd parameter 3 3 3 clk t rp trp parameter 3 3 3 clk
2 promos technologies v827464n24sc v827464n24sc rev. 1.2 april 2006 10 v 437432s24v rev. 1.0 june 2003 part number information this 512mb registered ecc ddr dimm is available in four different heights: 1.7", 1.2", 1.125", and 1.0". please refer to pages 12 to 15 for the detailed mechanical diagrams of all four pcb heights. low profile module (1.2 in) fbga-based low profile module (1.125 in) 1234567 8 9 101112 13 14 151617 v827464 n 2 4s c i x -d3 data pcb type promos depth g : gold_lead plating 16 : 16mb refresh component w : gold_rohs type 32 : 32 mb rate rev level l : low profile_lead plating 8 : ddr 64 : 64 mb 0: 4k x : low profile_rohs 65 : 128 mb 2: 8k 66 : 256 mb voltage component pkg 2 : 2.5v lead green package data width banks plating description & comp density 4 : 4 banks t i tsop 65 x64 using 128m s j fbga 66 x64 using 256m module type d n die-stacked tsop 67 x64 using 512m & comp width z p die-stacked fbga 68 x64 using 1g based on x4 x16 x8 69 x64 using 2g 184pin dimm 73 x72 using 128m unbuffered i/o interface speed 74 x72 using 256m 184pin dimm s: sstl_2 b0 : pc2100b (133mhz @cl2.5-3-3) 75 x72 using 512m registered b1 : pc2100a (133mhz @cl2-2-2) 76 x72 using 1g 200pin c0 : pc2700 (166mhz @cl2.5-3-3) 77 x72 using 2g so-dimm d0 : pc3200 (200mhz @cl2.5-3-3) 172pin d3 : pc3200 (200mhz @cl3-3-3) micro-dimm *rohs: restriction of hazardous substances *green: rohs-compliant and halogen-free m k u g ij no vb
promos technologies v827464n24sc 3 v827464n24sc rev. 1.2 april 2006 block diagram dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dqs0 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dqs9 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dqs11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dqs12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dqs13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dqs14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dqs16 rs 0 dqs4 dqs1 dqs5 dqs2 dqs3 dqs15 dqs6 dqs7 dq15 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dqs8 dqs17 ras cas cke0 ba0-ban a0-a13 s0 rs0b rs0a rba0 - rban ra0 - ra12 rras rcas rcke0a rwe rcke0b ba0 -ban : sdrams dq0 - d17 a0 -an : sdrams d0 - d17 ras : sdrams d0 - d17 cas : sdrams dq0 - d17 cke : sdrams d0 - d8 cke : sdrams d9 - d17 we : sdrams d0 - d17 r e g i s t e r dqs i/o 3 i/o 2 i/o 1 i/o 0 d8 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d0 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d1 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d2 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d3 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d4 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d5 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d6 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d7 cs dm vss dqs i/o 3 i/o 2 i/o 1 i/o 0 d17 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d9 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d10 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d11 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d12 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d13 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d14 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d15 cs dm dqs i/o 3 i/o 2 i/o 1 i/o 0 d16 cs dm dqs10 reset pck pck we a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss d0 - d17 d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref v ddspd spd (dm0) (dm1) (dm2) (dm3) (dm4) (dm5) (dm6) (dm7) (dm8)
4 promos technologies v827464n24sc v827464n24sc rev. 1.2 april 2006 pin configurations (front side/back side) pin front pin front pin front pin back pin back pin back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 vref dq0 vss dq1 dqs0 dq2 vdd dq3 nc nc vss dq8 dq9 dqs1 vddq ck1 ck1 vss dq10 dq11 cke0 vddq dq16 dq17 dqs2 vss a9 dq18 a7 vddq dq19 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 a5 dq24 vss dq25 dqs3 a4 vdd dq26 dq27 a2 vss a1 cb0* cb1* vdd dqs8* a0 cb2* vss cb3* ba1 key dq32 vddq dq33 dqs4 dq34 vss ba0 dq35 dq40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 vddq we dq41 cas vss dqs5 dq42 dq43 vdd nc dq48 dq49 vss ck2 ck2 vddq dqs6 dq50 dq51 vss vddid dq56 dq57 vdd dqs7 dq58 dq59 vss nc sda scl 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 vss dq4 dq5 vddq dm0 dq6 dq7 vss nc nc a13* vddq dq12 dq13 dm1 vdd dq14 dq15 cke1 vddq ba2* dq20 a12 vss dq21 a11 dm2 vdd dq22 a8 dq23 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 vss a6 dq28 dq29 vddq dm3 a3 dq30 vss dq31 cb4* cb5* vddq ck0* ck0 * vss dm8* a10 cb6* vddq cb7* key vss dq36 dq37 vdd dm4 dq38 dq39 vss dq44 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 ras dq45 vddq cs0 cs1 dm5 vss dq46 dq47 nc vddq dq52 dq53 nc vdd dm6 dq54 dq55 vddq nc dq60 dq61 vss dm7 dq62 dq63 vddq sa0 sa1 sa2 vddspd notes: * these pins are not used in this module. pin names pin pin description ck1, ck1 , ck2, ck2 differential clock inputs cs0 chip select input cke0 clock enable input ras , cas , we commend sets inputs a0 ~ a12 address ba0, ba1 bank address dq0~dq63 data inputs/outputs dqs0~dqs7 data strobe inputs/outputs dm0~dm7 data-in mask key key vdd power supply vddq dqs power supply vss ground vref reference power supply vddspd power supply for spd sa0~sa2 e 2 prom address inputs scl e 2 prom clock sda e 2 prom data i/o vddid vdd identification flag du do not use nc no connection pin pin description
promos technologies v827464n24sc 5 v827464n24sc rev. 1.2 april 2006 serial presence detect information bin sort: d0 (pc3200 @ cl 2.5-3-3) d3 (pc3200 @ cl 3-3-3 ) c0 (pc2700 @ cl 2.5-3-3) byte # function described function supported hex value d0 d3 c0 d0 d3 c0 0 defines # of bytes written into serial memory at module manufacturer 128bytes 80h 1 total # of bytes of spd memory device 256bytes 08h 2 fundamental memory type sdram ddr 07h 3 # of row address on this assembly 13 0dh 4 # of column address on this assembly 11 0bh 5 # of module rows on this assembly 1 bank 01h 6 data width of this assembly 72 bits 48h 7 .........data width of this assembly - 00h 8 vddq and interface standard of this assembly sstl 2.5v 04h 9 ddr sdram cycle time at cas latency =2.5 5ns 5ns 6ns 50h 50h 60h 10 ddr sdram access time from clock at cl=2.5 0.65ns 0.65ns 0.70ns 65h 65h 70h 11 dimm configuration type(non-parity, parity, ecc) non-parity, ecc 02h 12 refresh rate & type 7.8us & self refresh 82h 13 primary ddr sdram width x4 04h 14 error checking ddr sdram data width x4 04h 15 minimum clock delay for back-to-back random column address t ccd =1clk 01h 16 ddr sdram device attributes : burst lengths supported 2,4,8 0eh 17 ddr sdram device attributes : # of banks on each ddr sdram 4 banks 04h 18 ddr sdram device attributes : cas latency supported 2,2.5,3 0ch 1ch 1ch 19 ddr sdram device attributes : cs latency 0clk 01h 20 ddr sdram device attributes : we latency 1clk 02h 21 ddr sdram module attributes registered address & control inputs and on-card dll 26h 22 ddr sdram device attributes : general +/-0.2v voltage tolerance 00h 23 ddr sdram cycle time at cl =2 5.0ns 6.0ns 7.5ns 50h 60h 75h 24 ddr sdram access time from clock at cl =2 0.65ns 0.70ns 0.70ns 65h 70h 70h 25 ddr sdram cycle time at cl =1.5 7.5ns 7.5ns - 75h 75h 00h 26 ddr sdram access time from clock at cl =1.5 0.75ns 0.75ns - 75h 75h 00h 27 minimum row precharge time (=t rp ) 15ns 15ns 18ns 3ch 3ch 48h
6 promos technologies v827464n24sc v827464n24sc rev. 1.2 april 2006 28 minimum row activate to row active delay (=t rrd ) 10ns 10ns 12ns 28h 28h 30h 29 minimum ras to cas delay (=t rcd ) 15ns 15ns 18ns 3ch 3ch 48h 30 minimum active to precharge time (=t ras ) 40ns 40ns 42ns 28h 28h 2ah 31 module row density 512mb 80h 32 command and address signal input setup time 0.6ns 0.6ns 0.75ns 60h 60h 75h 33 command and address signal input hold time 0.6ns 0.6ns 0.75ns 60h 60h 75h 34 data signal input setup time 0.4ns 0.4ns 0.45ns 40h 40h 45h 35 data signal input hold time 0.4ns 0.4ns 0.45ns 40h 40h 45h 36-40 superset information (may be used in future) - 00h 41 sdram device minimum active to active/auto-refresh time (=t rc ) 60ns 60ns 60ns 3ch 3ch 3ch 42 sdram device minimum active to autorefresh to active/ auto-refresh time (=t rfc ) 70ns 70ns 72ns 46h 46h 48h 43 sdram device maximum device cycle time (=t ck max ) 12ns 12ns 12ns 30h 30h 30h 44 sdram device maximum skew between dqs and dq sig- nals (=t dqsq ) 0.4ns 0.4ns 0.45ns 28h 28h 2dh 45 sdram device maximum read datahold skew factor (=t qhs ) 0.55ns 0.55ns 0.60ns 55h 55h 60h 46 - 61 superset information (may be used in future) - 00h 62 spd data revision code initial release 00h 11h 11h 63 checksum for bytes 0 ~ 62 - f4h 0fh 9ch 64 manufacturer jedec id code promos 40h 65 -71 ....... manufacturer jedec id code 00h 72 manufacturing location 02=taiwan 05=china 0a=s-ch 73-90 module part number (ascii) v827464n24sc 91 manufacturer revison code (for pcb) 0 00 92 manufacturer revison code (for component) 0 00 93 manufacturing date (year) - - 94 manufacturing date (week) - - 95~98 assembly serial # - - 99~127 manufacturer specific data (may be used in future) undefined 00h 128~255 open for customer use undefined 00h byte # function described function supported hex value d0 d3 c0 d0 d3 c0 serial presence detect information (cont.)
promos technologies v827464n24sc 7 v827464n24sc rev. 1.2 april 2006 dc operating conditions (t a = 0 to 70c, voltage referenced to v ss = 0v) notes: 1. v ddq must not exceed the level of v dd . 2. v il (min) is acceptable -1.5v ac pulse width with <= 5ns of duration. ac operating conditions (t a = 0 to 70 c, voltage referenced to v ss = 0v) notes: 1. vid is the magnitude of the difference between the input level on ck and the input on ck. 2. the value of vix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. parameter symbol min typ. max unit note power supply voltage v dd 2.3 2.5 2.7 v power supply voltage v ddq 2.3 2.5 2.7 v 1 input high voltage v ih v ref + 0.15 - v ddq + 0.3 v input low voltage v il -0.3 - v ref - 0.15 v 2 i/o termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v reference voltage v ref 1.15 1.25 1.35 v input leakage current i i -2 - 2 a output leakage current io z -5 - 5 a output high current (v out = 1.95v) io h -16.8 - - ma output low current (v out = 0.35v) io l 16.8 - - ma parameter symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals v ih(ac) v ref + 0.31 v input low (logic 0) voltage, dq, dqs and dm signals v il(ac) v ref - 0.31 v input differential voltage, ck and ck inputs v id(ac) 0.7 v ddq + 0.6 v 1 input crossing point voltage, ck and ck inputs v ix(ac) 0.5*v ddq-0.2 0.5*v ddq+0.2 v2
8 promos technologies v827464n24sc v827464n24sc rev. 1.2 april 2006 ac operating test conditions (t a = 0 to 70c, voltage referenced to v ss = 0v) input/output capacitance (v dd = 2.5v, v ddq = 2.5v, t a = 25c, f = 1mhz) parameter value unit reference voltage v ddq x 0.5 v termination voltage v ddq x 0.5 v ac input high level voltage (v ih , min) v ref + 0.31 v ac input low level voltage (v il , max) v ref - 0.31 v input timing measurement reference level voltage v ref v output timing measurement reference level voltage v tt v input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns termination resistor (r t ) 50 ohm series resistor (r s ) 25 ohm output load capacitance for access time measurement (c l ) 30 pf parameter symbol min max unit input capacitance (a 0 ~ a 11 , ba 0 ~ ba 1 , ras , cas , we ) cin 1 60 75 pf input capacitance (cke 0 ) cin 2 40 48 pf input capacitance (cs 0 ) cin 3 40 48 pf input capacitance (clk 1 , clk 2 ) cin 4 30 32 pf data & dqs input/output capacitance (dq 0 ~dq 63 ) c out 10 12 pf input capacitance (dm0~dm8) cin 5 10 12 pf output load circuit (sstl_2) o utput z0=50 ? c load =30pf v ref =0.5*v dd q r t =50 ? v tt =0.5*v ddq
promos technologies v827464n24sc 9 v827464n24sc rev. 1.2 april 2006 ddr sdram i dd spec table * module i dd was calculated on the basis of component i dd and can be differently measured according to dq loading cap. detailed test conditions for ddr sdram idd1 & idd idd1 : operating current: one bank operation 1. typical case : vdd = 2.5v, t=25? c 2. worst case : vdd = 2.7v, t= 10? c 3. only one bank is accessed with trc(min), burst mode, address and control inputs on nop edge are changing once per clock cycle. lout = 0ma 4. timing patterns - ddr333 (166mhz, cl=2.5) : tck=6ns, cl=2.5, bl=4, trcd=3*tck, trc=10*tck, tras=7*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing *50% of data changing at every burst - ddr400b (200mhz, cl=3) : tck=5ns, cl=3, bl=4, trcd=3*tck, trc=12*tck, tras=8*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing *50% of data changing at every burst - ddr400a (200mhz, cl=2.5) : tck=5ns, cl=2.5, bl=4, trcd=3*tck, trc=12*tck, tras=8*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing *50% of data changing at every burst legend : a=activate, r=read, w=write, p=precharge, n=nop symbol d0 / d3 pc3200a@ cl=3 c0 pc2700a@ cl=2.5 unit idd0 1100 990 ma idd1 1340 1260 ma idd2p 500 450 ma idd2f 450 405 ma idd2q 350 396 ma idd3p 500 450 ma idd3n 800 720 ma idd4r 2300 2070 ma idd4w 2100 1890 ma idd5 1900 1800 ma idd6 normal 54 54 ma low power 33 33 ma idd7 3200 3150 ma
10 promos technologies v827464n24sc v827464n24sc rev. 1.2 april 2006 ac characteristics (ac operating conditions unless otherwise noted) parameter symbol ddr400a d0 ddr400b d3 ddr333 c0 unit note min max min max min max row cycle time t rc 60 - 60 - 60 - ns auto refresh row cycle time t rfc 70 - 70 - 72 - ns row active time t ras 40 120k 40 120k 42 120k ns row address to column address delay t rcd 15 - 15 - 18 - ns row active to row active delay t rrd 10 - 10 - 12 - ns column address to column address delay t ccd 1 - 1 - 1 - clk row precharge time t rp 15 - 15 - 18 - ns write recovery time t wr 15 - 15 - 12 - ns last data-in to read command t drl 1 - 1 - 1 - clk auto precharge write recovery + precharge time t dal 35 - 35 - 35 - ns system clock cycle time cas latency = 3 t ck 512512 - - ns cas latency = 2.5 5 12 6 12 6 12 ns cas latency = 2 7.5 12 7.5 12 7.5 12 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 clk clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 clk data-out edge to clock edge skew t ac 0.45 0.55 0.45 0.55 -0.75 0.75 ns dqs-out edge to clock edge skew t dqsck -0.65 0.65 -0.65 0.65 -0.75 0.75 ns dqs-out edge to data-out edge skew t dqsq -0.60 0.60 -0.60 0.60 - 0.45 ns data-out hold time from dqs t qh - 0.40 - 0.40 t hpmin -0.75ns - ns 1 clock half period t hp t hpmin -0.75ns - t hpmin -0.75ns - t ch/l min - ns 1 input setup time (fast slew rate) t is t ch/l min - t ch/l min - 0.75 - ns 2,3,5,6 input hold time (fast slew rate) t ih 0.6 - 0.6 - 0.75 - ns 2,3,5,6 input setup time (slow slew rate) t is 0.6 - 0.6 - 0.8 - ns 2,4,5,6 input hold time (slow slew rate) t ih 0.75 - 0.75 - 0.8 - ns 2,4,5,6 input pulse width t ipw 0.75 - 0.75 - 0.4 0.6 ns 6 write dqs high level width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 clk write dqs low level width t dqsl 0.35 0.35 0.75 1.25 clk clk to first rising edge of dqs-in t dqss 0.35 0.35 0.45 - clk data-in setup time to dqs-in (dq & dm) t ds 0.72 1.25 0.72 1.25 0.45 - ns 7 data-in hold time to dqs-in (dq & dm) t dh 0.40 - 0.40 - 1.75 - ns 7 dq & dm input pulse width t dipw 1.75 - 1.75 - 0.9 1.1 ns
promos technologies v827464n24sc 11 v827464n24sc rev. 1.2 april 2006 ac characteristics (cont.) notes: 1. this calculation accounts for tdqsq(max), the pulse width distortion of on-chip circuit and jitter. 2. data sampled at the rising edges of the clock : a0~a11, ba0~ba1, cke, cs , ras , cas , we . 3. for command/address input slew rate >=1.0v/ns 4. for command/address input slew rate >=0.5v/ns and <1.0v/ns 5. ck, ck slew rates are >=1.0v/ns 6. these parameters guarantee device timing, but they are not necessarily tested on each dev ice, and they may be guaranteed by design or tester correlation. 7. data latched at both rising and falling edges of data strobes(dqs) : dq, dm 8. minimum of 200 cycles of stable input clocks after self refresh exit command, where cke is held high, is required to complet e self refresh exit and lock the internal dll circuit of ddr sdram. absolute maximum ratings note: operation at above absolute maximum rati ng can adversely affect device reliability read dqs preamble time t rpre 0.9 1.1 0.9 1.1 0.4 0.6 clk read dqs postamble time t rpst 0.4 0.6 0.4 0.6 0 - clk write dqs preamble setup time t wpres 0 - 0 - 0.25 - clk write dqs preamble hold time t wpreh 0.25 - 0.25 - 0.4 0.6 clk write dqs postamble time t wpst 0.4 0.6 0.4 0.6 2 - clk mode register set delay t mrd 2- 2- 10 - clk power down exit time t pdex 1 - 1 - 75 - ns exit self refresh to non-read command t xsnr 75 - 75 - 75 - ns exit self refresh to read command t xsrd 200 - 200 - 200 - clk 8 average periodic refresh interval t refi - 7.8 - 7.8 - 7.8 us parameter symbol rating unit ambient temperature t a 0 ~ 70 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd relative to v ss v dd -0.5 ~ 3.6 v voltage on v ddq relative to v ss v ddq -0.5 ~ 3.6 v output short circuit current i os 50 ma power dissipation p d 8 w soldering temperature ? time t solder 260 ? 10 c ? sec parameter symbol ddr400a d0 ddr400b d3 ddr333 c0 unit note min max min max min max
12 promos technologies v827464n24sc v827464n24sc rev. 1.2 april 2006 module dimensions (standard v827464n24sxtg) note: 1. all dimensions in inches (millimeters) max or typical where noted. min 1.705 (43.31) 1.695 (43.05) pin 1 .700 (17.78) typ. .098 (2.50) d (2x) .091 (2.30) typ. .250 (6.35) typ. 4.750 (120.65) .050 (1.27) typ. .091 (2.30) typ. .040 (1.02) typ. .079 (2.00) r (4x) .035 (0.90) r pin 92 front view .054 (1.37) .046 (1.17) 5.256 (133.50) 5.244 (133.20) 2.55 (64.77) 1.95 (49.53) .394 (10.00) typ. .125 (3.175) max back view pin 184 pin 93 u1 u2 u3 u4 u5 u11 u12 u6 u7 u13 u8 u9 u10 u14 u15 u16 u17 u18 u19 u20 u21 u22
promos technologies v827464n24sc 13 v827464n24sc rev. 1.2 april 2006 module dimensions (low profile1 v827464n24sxtl) note: 1. all dimensions in inches (millimeters) max or typical where noted. min u1 u2 u3 u4 u11 u12 u5 u6 u7 u8 u9 u14 u15 u16 u17 u18 u13 u10 u19 u20 u21 u22 .054 (1.37) .046 (1.17) .125 (3.175) max 1.205 (30.61) 1.195 (30.35) pin 1 .700 (17.78) typ. .098 (2.50) d (2x) .091 (2.30) typ. .250 (6.35) typ. 4.750 (120.65) .050 (1.27) typ. .091 (2.30) typ. .040 (1.02) typ. .079 (2.00) r (4x) .035 (0.90) r pin 92 front view 5.256 (133.50) 5.244 (133.20) 2.55 (64.77) 1.95 (49.53) .394 (10.00) typ. back view pin 184 pin 93
14 promos technologies v827464n24sc v827464n24sc rev. 1.2 april 2006 module dimensions (low profile2 fbga-based v827464n24sxsg) .054 (1.37) .046 (1.17) .125 (3.175 ) max 1.125 (28.58) pin 1 .700 (17.78) typ. .098 (2.50) d (2x) .091 (2.30) typ. .250 (6.35) typ. 4.750 (120.65) .050 (1.27) typ. .091 (2.30) typ. .040 (1.02) typ. .079 (2.00) r (4x) .035 (0.90) r pin 92 front view 5.256 (133.50) 5.244 (133.20) 2.55 (64.77) 1.95 (49.53) .394 (10.00) typ. back view pin 184 pin 93 u1 u2 u3 u4 u5 u8 u9 u10 u11 u22 u21 u22 u19 u17 u16 u15 u14 u13 typ. note: 1. all dimensions in inches (millimeters) max or typical where noted. min
promos technologies v827464n24sc 15 v827464n24sc rev. 1.2 april 2006 module dimensions (low profile3 fbga-based v827464n24sxsl) .054 (1.37) .046 (1.17) .125 (3.175 ) max 1.000 (25.40) pin 1 .700 (17.78) typ. .098 (2.50) d (2x) .091 (2.30) typ. .250 (6.35) typ. 4.750 (120.65) .050 (1.27) typ. .091 (2.30) typ. .040 (1.02) typ. .079 (2.00) r (4x) .035 (0.90) r pin 92 front view 5.256 (133.50) 5.244 (133.20) 2.55 (64.77) 1.95 (49.53) .394 (10.00) typ. back view pin 184 pin 93 u1 u2 u3 u4 u5 u8 u9 u10 u11 u22 u21 u22 u19 u17 u16 u15 u14 u13 typ. note: 1. all dimensions in inches (millimeters) max or typical where noted. min
16 promos technologies v827464n24sc v827464n24sc rev. 1.2 april 2006 label information module density cas latency part number criteria of pc3200, pc2700 dimm manufacture date code c l = 2.5 (clk) t rcd = 3 (clk) t rp = 3 (clk) 2533 r registered dimm pcxxxx 0 spd revision x -- x - gerber file used for this design "a" : reference design for raw card a is used for this assembly "b" : reference design for raw card b is used for this assembly "c" : reference design for raw card c is used for this assembly "z" : none of the reference design were used for this assembly revision number of the reference design used "1" : 1st revision "2" : 2nd revision blank : not applicable promos technologies v827464n24sxxx-xx 512mb ddr-xxxmhz - clxx pcxxxxr-2533-0-xx xxxx-xxxxxxx assembly in taiwan
promos technologies v827464n24sc 17 v827464n24sc rev. 1.2 april 2006 worldwide offices ? copyright ,promos technology. printed in u.s.a. the information in this document is subject to change without notice. promos tech makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of promos tech. promos tech subjects its products to normal quality control sampling techniques which are intended to provide an assuranc e of high quality products suitable for usual commercial applica - tions. promos tech does not do testing appropriate to provide 100% product quality assurance and does not assume any liab il- ity for consequential or incidental arising from any use of its prod - ucts. if such products are to be used in applications in whic h personal injury might occur from failure, purchaser must do i ts own quality assurance testing appropriate to such applications. taiwan(taipei) 7f, no. 102 min-chuan e. road sec. 3, taipei, taiwan, r.o.c phone: 886-2-2545-1213 fax: 886-2-2545-1209 no. 19 li hsin road science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-566-3952 fax: 886-3-578-6028 japan onze 1852 building 6f 2-14-6 shintomi, chuo-ku tokyo 104-0041 phone: 81-3-3537-1400 fax: 81-3-3537-1402 usa(west) 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 sales offices: taiwan(hsinchu) usa(east) 25 creekside road hopewell jct, ny 12533 phone:845-223-1689 fax:845-223-1684

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